This invention relates to a circuit for compensating variation in delay time of a delay circuit due to temperature change. The circuit realizes a simplified circuit design by utilizing a signal treated in the delay circuit for an compensating operation.
A delay circuit is used in, for example, a video disc playback device for pulse-FM-detection of a video signal or an audio signal. In a pulse-FM-detection circuit 1, as shown in FIG. 2, a pulse frequency-modulated signal and a signal derived by delaying this signal for a predetermined period of time by a delay circuit 11 are applied to an exclusive OR gate 13 and an output of the exclusive OR gate 13 is integrated by an integration circuit 15. FIG. 3 shows the operation of this pulse-FM-detection circuit 1.
For the delay circuit 11, a circuit which utilizes a signal delaying characteristic of a gate circuit of a CMOS inverter, for example, may be used. The CMOS inverter is a circuit in which, as shown in FIG. 5, gates and drains of a p-channel MOS-FET 12 and an n-channel MOS-FET 14 are respectively connected to each other and power voltages V.sub.DD and V.sub.SS are applied to the sources of these MOS-FETs 12 and 14. In the CMOS inverter 10, a signal is applied to the gate through an input terminal 16 and an inverted signal of the input signal is provided from the drain to an output terminal 18.
In this CMOS inverter 10, a delay time is produced between the input and output. This delay time depends, as shown in FIG. 6, upon the power voltage V.sub.DD -V.sub.SS, namely the smaller the power voltage V.sub.DD -V.sub.SS, the longer is the delay time and the larger is the rate of change of the delay time. This is due to the fact that conductance of the circuit elements is caused to change by the power voltage V.sub.DD -V.sub.SS.
Delay time of about 3 ns to 5 ns is obtained per each CMOS inverter 10 so that a longer delay time can be obtained by cascade-connecting plural CMOS inverters 10.
As shown in FIG. 6, the delay time of the CMOS inverter 10 is subject to variation due to change in the ambient temperature. If there is variation in the delay time due to the temperature, accuracy of the pulse FM detection is deteriorated.
For improving such delay time-temperature characteristic of the delay circuit utilizing a CMOS inverter, efforts have been made for improving the temperature characteristic of the component elements of the CMOS inverter itself.
An alternative proposal for improving the delay time-temperature characteristic is made in Japanese Patent application No. 160785/1984 (Preliminary Publication No. 39722/1986). The circuit disclosed in this application is shown in FIG. 7. In this circuit, a ring oscillator 20 utilizes the delay characteristic of the CMOS inverter shown in FIG. 5 and is constructed of CMOS inverters of an odd number 22, 24 and 26 connected in cascade-connection with an output of the final stage CMOS inverter 26 being applied to the initial stage CMOS inverter 22. The oscillation frequency of the ring oscillator 20 is determined by the delay time of its open loop. The oscillation output of the ring oscillator 20 is waveshaped by a CMOS inverter 28 and thereafter is applied to a comparator 30. The comparator 30 compares, in frequency and phase, this signal with a reference frequency singal obtained by frequency-dividing an output pulse of a quartz oscillator 32 by a frequency divider 34 and thereupon produces a signal of a pulse width corresponding to difference between the two signals compared with each other.
A control voltage generation circuit 36 generates dc voltages V.sub.DD and V.sub.SS by smoothing the output pulse of the comparator 30. These dc voltages V.sub.DD and V.sub.SS are applied to the CMOS inverters 22, 24 and 26 constituting the ring oscillator 20. Since the delay characteristics of the CMOS inverters 22, 24 and 26 depend upon voltage applied thereto as described above, a highly stable oscillation frequency (with accuracy of the reference frequency) can be obtained from the ring oscillator 20 by contructing a PLL (phase-locked loop) by forming the above described loop as a negative feedback loop. That is, the delay time of the respective CMOS inverters 22, 24 and 26 are controlled to a constant delay time. By disposing the pulse FM detection circuit 1 shown in FIG. 2 in the same environment as the inverters 22, 24 and 26 (e.g., the same substrate of an integrated circuit) and applying the control voltages V.sub.DD and V.sub.SS obtained by the control voltage generation circuit 36 to the pulse FM detection circuit 1, variation in the delay time due to temperature change in this pulse FM detection circuit 1 can be eliminated.
The FM detection circuit of FIG. 2, the delay circuit of FIG. 5 and the temperature compensation circuit for a delay circuit shown in FIG. 7 are respectively disclosed in the specification of the U.S. patent application Ser. No. 760,332 filed July 29, 1985.
In the prior art temperature compensation circuit in which the temperature compensation is realized by improving the temperature characteristics of the component elements of the CMOS inverter itself, extra labor and cost are incurred for selection of material of the component elements of the CMOS inverter and processing of the material for imparting necessary characteristics to it and, besides, it has been found that the improvement achieved is of a limited degree.
The prior art circuit shown in FIG. 7 is meritorious in that it performs an active compensation by utilizing the electrical loop which can realize a temperature compensation which is constantly accurate regardless of characteristics of the component elements. This curcuit, however, additionally requires the ring oscillator 20 and the quartz oscillator 32 so that this circuit has the disadvantage that the circuit design becomes very complicated and costly.
It is, therefore, an object of the invention to provide a temperature compensation circuit for a delay circuit capable of realizing an active temperature compensation using an electric loop with a simplified circuit construction.